Data processing devices typically employ bus master modules that communicate with peripheral modules in the device. For example, a bus master of the data processing device can communicate with a peripheral module by writing data to or reading data from registers of the peripheral module via a data bus. To ensure proper operation of the data processing device, in some instances data is written to or read from the peripheral module registers coherently, so that all the data associated with an access request is read from or written to the register simultaneously, rather than in portions. For example, a register may contain information, such as timing information, that changes rapidly. If a first portion of the information is read at a first time from the register, and a second portion of the information is read at a later time, the two portions will no longer be coherent if the second portion has changed. However, in some devices, the size of the peripheral device registers exceeds the size of the data bus, requiring multiple data transfers over the data bus to access all of the data for a register, making it difficult to maintain coherency. To preserve coherency, each coherent access register can include its own shadow register. However, this effectively doubles the amount of register space required for each coherent access register.
Accordingly, it will be appreciated that an improved device and methods for performing coherent accesses would be advantageous.